Dissertation Defense Yichun Sun

Ph.D. Dissertation Defense Annoucement
Yichun Sun (ECE)

Title: Computer Architectures using Nanotechnology

Committee Members: Prof. Meghanad Wagh (Ph.D Advisor)
Prof. Zhiyuan Yan
Prof. Miltiadis Hatalis
Dr. Viswanath Annampedu (LSI)
Location and Time: 3:00 pm, October 24th 2011 (Monday)
Packard Lab 416


According to the International Technology Roadmap for Semiconductors, the emerging research devices such as Resonant Tunneling Diodes/Transistors (RTD/RTT), Single Electron Transistors(SET) and Quantum Cellular Automata (QCA) are expected to start replacing the CMOS devices in many applications by the end of the next decade. unfortunately, these new technologies cannot implement the traditional Boolean logic efficiently. On the other hand, they are well suited for threshold logic. Clearly, along with the development of the new devices, one should also explore the new design techniques that are compatible with these devices. This talk focuses on the development of stategies for design and implementation of computer architectures with nanotechnology. Recent studies have demonstrated that the reliability of a nanoelectronic logic gate is dependent upon its fan-in. All the designs presented in this talk therefore employ bounded fan-in threshold logic. We develop general schemes to decompose any threshold function into a network of threshold gates with bounded fan-in using a k-ary tree structure. For some applications, e.g., comparison function, the decomposition scheme leads to a circuit that has a lower complexity and higher speed. A new strategy to design adders which form the fundamental logic block of any computational unit will be discussed. This strategy allows one to design adders with required speed and complexity using threshold gates with a given fan-in bound. We show that by exploiting the properties of threshold functions, one can get new adder architectures that are much faster and far less complex than the Group Carry Look-ahead Adders (GCLA) presently employed in most modern processors. Our strategies also allow us a three-way trade-off between the hardware complexity, the reliability and the speed. Different implementation styles with nanoelectronic threshold gates will also be presented. We show that a systolic implementation of threshold logic can allows one to implement circuits with extremely low hardware complexity but with some loss of speed. We also develop designs using only majority gates which are well suited for Quantum-Dot Cellular Automata (QCA) technology.